A complex integrated circuit may contain millions of electronic components such as transistors, resistors, and capacitors. The design of such a complex integrated circuit may involve multiple teams of engineers. It is advantageous to partition the design of such complex integrated circuit using a hierarchical approach, whereby certain circuit components are grouped together and may be reused repeatedly through the integrated circuit or in a subsequent design. A method for design and simulation of an integrated circuit with a hierarchical data structure is disclosed by U.S. patent application Ser. No. 10/724,277, entitled “System and Method for Simulating a Circuit Having Hierarchical Structure”, filed on Nov. 26, 2003, which is incorporated expressly by reference in its entirety herein.
FIG. 1a illustrates an example of a chain of six inverters in a circuit design. The chain of inverters couples to each other back-to-back. At the highest level of the hierarchical netlist, the root level, the chain of inverters includes an input power signal Vin, a chain of six inverters X1 (Level 1), a power supply V1 coupled to the Vdd terminals of the inverters, and a capacitor load Cload coupled to the output of the chain of six inverters X1. An instance name of the chain of six inverters is X1. At Level 1, the chain of inverters may be grouped into three groups of subcircuits, namely X11, X12, X13 (Sub2), and each group of Sub2 is coupled to the next group of Sub2 through the net T1 or T2 as shown in FIG. 1a. At Level 2, each Sub2 circuit includes two inverters coupled back-to-back via the net T1. Each inverter comprises an input net A, an output net Y, a PMOS transistor Mp, and an NMOS transistor Mn.
FIG. 1b illustrates a hierarchical representation of the chain of inverters of FIG. 1a according to an embodiment of the present invention. At the root level, also referred to as Level 0, the components Vin, V1, Cload, and the ports In, Out, Vdd and 0 (Gnd) are connected as shown. In addition, the root level includes a reference to Level 1 though a call function having a set of call parameters (In, Out, Vdd, 0). At Level 1, the call parameters from the root level are received at a port having a corresponding set of parameters (In, Out, Vdd, 0). The subcircuits X11, X12, X13 are connected via the nodes In, T1, Vdd, 0, T2 and Out respectively. Level 1 includes references to Level 2 through three call functions originating from subcircuits X11, X12, and X13. Each of the call functions of subcircuits X11, X12, and X13 has a set of parameters (In, Out, Vdd, 0). Similarly at Level 2, the call parameters from Level 1 are received at a port having a corresponding set of parameters (In, Out, Vdd, 0). The subcircuits X21 and X22 are connected via the nodes In, T1, Out, Vdd, and 0 respectively. Level 2 includes references to an inverter (Level 3) through two call functions originating from subcircuits X21 and X22. Each of the call functions of subcircuits X21 and X22 has a set of parameters (In, Out, Vdd, 0). At Level 3, a single inverter formed by a PMOS transistor Mp and an NMOS transistor Mn, which is also referred to as a leaf circuit, is coupled to the nodes In, Out, Vdd, and 0 as shown in FIG. 1b. 
The hierarchical representation of the chain of six inverters as shown in FIG. 1b works well as a behavior model for design and simulation of the integrated circuit. However, it does not accurately represent all the physical aspects of the circuit after it is laid out and back-annotated as a flat netlist, which is also referred to as a gate-level netlist.
Existing circuit simulators simulate a back-annotated circuit, such as the chain of inverters of FIG. 1a, as a flat circuit. As a result, the performance of the simulation suffers significantly because of the large number of circuit components, such as the back-annotated parasitic resistors and capacitors, which have to be simulated. Additionally, simulating the flat netlist requires more memory because of the large number of circuit components of the back-annotated flat netlist. Therefore, there is a need for a system and method for converting a flat netlist into a hierarchical netlist for the simulation of a complex integrated circuit.